Semiconductors are widely used in integrated circuits for electronic applications, including high speed computers and wireless communications. Such integrated circuits typically use multiple transistors fabricated in single crystal silicon. Many integrated circuits now contain multiple levels of metallization for interconnections. A single semiconductor microchip may have thousands, and even millions of transistors. Logically, a single microchip may also have millions of lines interconnecting the transistors. As device geometries shrink and functional density increases, it becomes imperative to reduce the capacitance between the lines. Line-to-line capacitance can build up to a point where a delay time and crosstalk may hinder device performance. Reducing the capacitance within these multi-level metallization systems will reduce the RC constant, crosstalk voltage, and power dissipation between the lines. The material typically used to isolate metal lines from each other is silicon dioxide. Silicon dioxide is a thermally and chemically stable material. Conventional oxide etches are also available for high-aspect-ratio contacts and vias.
However, the dielectric constant of dense silicon oxide grown by thermal oxidation or chemical vapor deposition is on the order of 3.9. The dielectric constant is based on a scale where 1.0 represents the dielectric constant of a vacuum. As used herein, the term "low dielectric" will refer to a material with a dielectric constant less than 3.7.
Recently, attempts have been made to use low-density materials, such as aerogel, having a lower dielectric constant to replace dense silicon oxide. The dielectric constant of a porous silicon dioxide, such as aerogel, can be as low as 1.2. This lower dielectric constant results in a reduction in the RC delay time. However, the traditional method of making aerogel requires a supercritical drying step, which increases the cost and the degree of complexity for semiconductor manufacturing.